1. Field of the Invention
The present invention relates to the field of electronic design automation (EDA). More specifically, the present invention relates to EDA tools for parasitic extraction in the process of designing sub-micron integrated circuit.
2. Background Information
The technology of large scale integration continues to advance rapidly. Integrated circuits (IC) fabricated employing deep sub-micron processes are increasingly common and increasingly complex. One of the challenges faced by today's deep sub-micron IC designers is the issue of parasitic effects of passive interconnect. Deep sub-micron IC designers have come to recognize that these effects cannot be ignored, else the design can fail. These effects play an important role in timing, power, reliability as well as noise performance. In order to take parasitic effects of passive interconnect into consideration in post layout analysis for timing, power, etc., it is necessary to create electrical models for the physical connections present between the various devices in a deep sub-micron IC design, a process known as parasitic extraction. Multiple parasitic extractions performed repeatedly at different points in time to create multiple electrical models for different views of the design are often required.
With respect to parasitic extraction for deep sub-micron IC designs, conventional EDA tools typically suffer from at least four disadvantages.
(a) They do not support enough rich models to describe the increasingly complex processes; PA1 (b) They do not adequately address electrical interdependence between a physical net model and a design model; PA1 (c) They are incapable of dealing with the enormous data volumes generated by the increasingly complex deep sub-micron designs; and PA1 (d) They do not efficiently support concurrent use by multiple post-layout analysis tools.
Thus, a more effective and yet efficient approach to generating and storing electrical modeling data for a deep sub-micron IC design that are comprehensive and organized to meet the needs of post-layout analysis is desired.